The present invention is related to a low inductance capacitor having two terminals. More particularly, the present invention is related to a low inductance multi-layer capacitor having two terminals which electrically connect to the lead-out tabs of interleaved T shaped electrodes.
In summary, the art has been seeking a low inductance multi-layer capacitor for use in high frequency decoupling applications which is effective and inexpensive to manufacture, as well as simple to use. Recent developments in microprocessors and memory technologies have led to an increased demand for faster switching speeds and greater densities in integrated circuits. Because of these demands, higher operating frequencies or switching speeds are required which cause larger current fluctuations and difficulties in controlling voltage fluctuations accompanying these larger current fluctuations. Today, sophisticated noise filtering techniques are necessary to stabilize these fluctuations.
Decoupling capacitors are often used as a means of overcoming physical and time constraints found in integrated circuits by reducing voltage fluctuations and enhancing the reliability of the device. Commonly, multi-layer ceramic capacitors are used as decoupling capacitors because of their size, availability, density, performance, reliability, and cost. Decoupling capacitors are usually mounted on a printed circuit board (“PCB”) in close proximity to the decoupled microprocessor or integrated circuit. By supplying quick charge flow at the event of a high speed transient current fluctuation, the decoupling capacitor supplies a supplemental current, thereby reducing voltage fluctuation of the power source.
As switching speeds and device densities of integrated circuits increase, greater demands are placed on decoupling capacitors. In the past, this demand has been met through the use of larger and larger capacitance value capacitors. The use of larger value capacitors, however, creates two problems. First, there is an ongoing demand for smaller and smaller devices due to the ongoing desire for the miniaturization of electronic apparatuses. Second, the larger the capacitor size, the larger the parasitic inductance becomes. Parasitic inductance is almost always undesirable because it degrades the effectiveness of the capacitor. Capacitors with large parasitic inductances have relatively low resonance frequency combined with relatively high impedance at high frequencies making them unusable for many high-speed applications. The relationship between resonance frequency and capacitance can be expressed in the following equation:
      f    0    =      1          2      ⁢      π      ⁢              LC            wherein fo represents resonance frequency, L represents parasitic inductance, which is suitably estimated as equivalent series inductance (“ESL”), and C represents capacitance. As can be seen, the smaller the inductance L, the higher the resonance frequency fo becomes.
Mutual inductance is also undesirable in an electric circuit because it causes unwanted coupling between conductors in a circuit. Mutual inductance is the property of an electric circuit or component which generates an electromotive force (“EMF”). Mutual inductance occurs as a result of a change in the current flowing through a neighboring circuit with which it is magnetically linked. In other words, mutual inductance is the voltage induced in one circuit when the current in another circuit changes by a unit amount in unit time. The EMF generated by the presence of mutual inductance maintains a direction which is always opposite the change in the magnetic field.
Low inductance capacitors are known in the art. U.S. Pat. No. 6,950,300 to Sutardja (“the '300 patent”) discloses a multilayer capacitor having a low parasitic inductance. A sideways T shaped electrode is vertically oriented and mounted to a PCB. The T extensions are electrically connected to four separate external contact bars at the bottom and top of the capacitor. The distance between the two external contact bars at the top and bottom of the capacitor is reduced to decrease the parasitic inductance. While the '300 patent discloses a capacitor with lower parasitic inductance than standard multilayer capacitors, it does not disclose a capacitor with lower mutual inductance. Furthermore, the '300 patent still maintains a high parasitic inductance due to the limiting surface area of the terminations. The capacitors disclosed in the '300 patent are expensive to manufacture and have limiting mounting capabilities due to the use of separate external contact bar terminations. Furthermore, the external electrodes are only internally connected to the capacitor body.
U.S. Pat. No. 6,496,355 to Galvagni et al. (“the '355 patent”) discloses an improved low inductance interdigitated capacitor and corresponding termination scheme. The '355 patent discloses the use of solder stops to create a ball limiting metallurgy and provides for the use of electrode tabs extending from electrode layers which are exposed on the sides of the capacitor body. While the '355 patent provides for a lower parasitic and mutual inductance, both the parasitic and mutual inductance remain high because of the electrode configuration and orientation. Further, the '355 patent requires the use of solder stops and maintains limiting mounting capabilities.
U.S. Pat. No. 7,054,136 to Ritter et al. (“the '136 patent”) discloses a multilayer ceramic capacitor assembly capable of exhibiting low high-frequency inductance and a controlled ESR. The '136 patent teaches multi-layered termination wherein the multiple layers reduce thermal shock problems in the capacitor. The use of a serpentine design electrode element is also disclosed to enhance the ESR. The serpentine pattern disclosed in the '136 patent does not effectively reduce ESR because each electrode plate has a wide surface area when the current enters each electrode plate from the termination. Further, the capacitor has a high inductance due to, for example, the electrode configuration and the current passing through multiple faces on the capacitor.
Further multilayer capacitors also known in the art include U.S. Pat. No. 6,292,351 to Ahiko et al., and U.S. Pat. Nos. 6,956,730; 6,965,507; and 6,765,781 and U.S. Publication Nos. 2006/0028785 and 2005/0264977 all to Togashi. These patents do not disclose capacitors with low mutual inductance and provide for capacitors with high parasitic inductance due to the limiting surface area of the interdigitated external terminations. Moreover, the items described in these patents are expensive to manufacture because of the lack of symmetry of the internal electrodes and the limiting mounting capabilities due to the use of separate external contact bar terminations.
In summary, the art has been seeking a multi-layer capacitor which generates low parasitic and mutual inductance in decoupling applications, is compatible with most existing circuit boards, maintains electrode symmetry and which is easily mountable and inexpensive to manufacture.